The present invention relates to a semiconductor device and a method thereof, more particularly, to a semiconductor device using a semiconductor fin and a method thereof.
For the past 30 years, silicon based integrated circuit devices, especially, metal oxide semiconductor MOS devices such as electric field effect transistors FET or MOSFET have been manufactured to have a high speed, a high integration or improved functions, decreasing a cost per a work process, so-called a throughput. However, as more highly integrated devices continue to be requested in view of high performance, high speed, low power consumption and costs, there occur various problems including deteriorating characteristics of a transistor. For example, as a channel length of an electric field effect transistor becomes shorter, there occur short channel effects such as a punchthrough, a drain induced barrier lowering DIBL and a subthreshold swing, an increase of a parasite capacitance or a contact capacitance between a contact area and a substrate, an increase of a leakage currents, and so on.
Thus, a process for manufacturing a fin electric field effect transistor in which a channel is formed in a semiconductor fin, a gate insulating layer is formed on the semiconductor fin, and a gate electrode is formed surrounding the semiconductor fin has been suggested. A fin electric field effect transistor having a channel formed on the semiconductor fin can decrease a channel length less than 50 nm, for example, 10 nm. Therefore, an improvement of an additional integration density and a speed is expected.
A flash memory device as an electrically programmable non-volatile memory device can carry out a programming operation in a unit of page or multibits, and an erase operation in a unit of block or sector, and has very excellent characteristics in view of speed. The above flash memory device can be employed in various devices such as a digital mobile phone, a digital camera, a LANSwitch, a PC card in a notebook computer, a digital setTop box, a built-in controller and so on.
FIG. 1 schematically illustrates a conventional flash memory device. Referring to FIG. 1, the flash memory device includes a gate structure stacked on a substrate 11. The stacked structure includes a tunneling oxide layer 15, a floating gate electrode 17, a gate insulating layer 19 and a control gate electrode 21. A source region 13S and a drain region 13D are located on a substrate at both sides of the stacked gate structure. If an appropriate bias voltage is applied to the control gate electrode 21, the source region 13S, the drain region 13D and the substrate 11, the electrically isolated floating gate 17 is charged or discharged into charges, and a threshold voltage is changed into two levels. Therefore, the flash memory device can perform as a memory device capable of storing binary information.
In the meantime, in order to maintain a high capacity, a high speed, a low power consumption and low costs, a semiconductor device is continuously requested to be highly integrated. The floating gate electrode 15 can be charged or discharged with a Fowler-Nordheim tunneling (F-N tunneling) or a channel hot carrier injection CHCI. In a case of using the F-N tunneling method, a high voltage is applied to the control gate electrode 21 and the substrate 11, and the charges penetrate the tunneling insulating layer 13 to be accumulated on the floating gate electrode 15. Accordingly, the tunneling insulating layer 13 should be thin enough for a tunneling of charges. However, if the tunneling insulating layer 13 is too thin, the charges can penetrate the thin tunneling insulating layer even though a very low bias voltage or no bias voltage is applied in comparison with a programming or an erase operation. A limit in a thickness of the tunneling insulting layer 13 is operated as a factor disturbing the high integration of a flash memory device.
Thus, attempts to apply for a flash memory device using a semiconductor fin in a Complementary Metal Oxide Semiconductor CMOS device have been made, recently. For instance, a flash memory device using a semiconductor fin published No. 2003/0042531 A1 in the name of Jong-Ho LEE is disclosed under the title of “FLASH MEMORY ELEMENT AND MANUFACTURING METHOD THEREOF”. According to the disclosure, a semiconductor fin is formed using an oxide layer mask, and both side surfaces of the semiconductor fin is operated as an active region namely, a channel. The invention disclosed by Jong-Ho LEE is interested in scaling down a flash memory device.
However, an efficiency of a programming and an erase operation should be taken into consideration in conjunction with scaling down a flash memory device. This is closely related to a capacitive coupling of a floating gate electrode with respect to a control gate electrode and a substrate. FIG. 2 schematically illustrates a capacitive coupling of a floating gate electrode with respect to various terminals in a flash memory device. Capacitances between a floating gate and each of a control gate, a substrate, a source region and a drain region, respectively are represented as CONO, CTOX, CSRC and CDRN. Even not shown in the drawings, a capacitor component between the substrate and the floating gate electrode includes not only a component CTOX due to a tunneling oxide layer but also a component CFOX due to a field oxide layer. Accordingly, a capacitance in total CTOT is represented in the formula 1 as follows,CTOT=CONO+CTOX+CSRC+CDRN+CFOX  Formula 1
As an amount of charges QFG stored in the floating gate is not changed by a minute change of a bias with respect to various terminals, an amount of charges in total is represented in the formula 2 as follows,QFG=0=CONO(VFG−VG)+CSRC(VFG−VS)+CDRN(VFG−VD)+CTOX(VG−VSUB)   Formula 2
Here, it is assumed that a substrate bias is fixed, and the components CTOX and CFOX are ignored.
The floating gate electrode voltage VFG is indirectly determined by a coupling ratio due to a bias voltage applied to a control gate electrode, a drain and a source, and is represented in the formula 3 as follows,VFG=VG×GCR+VS×SCR+VD×DCR   Formula 3
Here, GCR=CONO/CTOT, DCR=CDRN/CTOT, and SCR=CSRC/CTOT.
Accordingly, it is known that a coupling ratio in each term in the right side of the formula 3 needs to be increased in order to increase a floating gate electrode voltage VFG having a direct influence on an efficiency of a programming or an erase operation. In particular, one method may be to increase a coupling ratio GCR with respect to the floating gate electrode due to a bias voltage VG applied to the control gate electrode. For this, CTOT should be lowered, and a capacitance contribution component CTOX due to a tunneling insulating layer needs to be increased.